1. Field of the Invention
The present invention relates generally to power supplies, and more particularly to a power supply configured to be connected in parallel to one or more power supplies so as to share with the other power supplies in supplying load current.
2. Description of the Related Art
In recent years, so-called POL (Point of Load), which puts small-capacity DC/DC converters (hereinafter simply referred to as DDCs) into parallel operation and places them in the immediate vicinity of a load, has been commonly employed instead of the conventional centralized power architecture as power supply configuration for large-scale server systems. At this point, in order to increase the reliability of the DDCs operating in parallel, a so-called current balance function that equalizes the output currents of the DDCs for thermal balance among the DDCs is provided. As this current balance function, the average current mode, in which a DDC compares its output current with that of another DDC and finely adjusts output voltage based on the comparison results, is widely used.
Meanwhile, in a system used in a mission critical environment, DDCs are used in the so-called N+1 parallel redundant mode, and the highest current mode, which makes it possible to maintain the current balance function even if one of the DDCs fails, is used. According to this N+1 parallel redundant mode (alternatively, also referred to as the N+1 parallel operation mode), another extra DDC is added to N DDCs necessary for a required power supply capacity on the load side so that the condition of the required power supply capacity can be satisfied even if one of the DDCs becomes unusable due to failure. Reference may be made to Japanese Laid-Open Patent Application No. 7-194118 (hereinafter, JP 7-194118) and Balogh, Laszlo; THE UC3902 LOAD SHARE CONTROLLER AND ITS PERFORMANCE IN DISTRIBUTED POWER SYSTEMS, APPLICATION NOTE U-163, Unitrode Corporation (hereinafter, Balogh) for the conventional technology.
In a unit-type DDC used in the conventional centralized power architecture, the inductance of a bus bar connecting a power supply and a load is high, so that a large load capacitor is provided in the vicinity of the load. This capacitor absorbs sharp variations in load current, so that the output current of the DDC has a low-frequency sinusoidal waveform from which high frequency components are removed.
Nowadays, however, according to POL, this bus bar is omitted, the DDC is responsive at higher speed, and the load capacitor is reduced. As a result, the output current of the DDC tends to vary sharply so as to include a lot of high frequency components. This sharp variation in the output current affects a current balance circuit of Highest Current Mode, so that the problem of increasing output voltage tends to occur. In particular, this problem is prominent in a DDC for memory, in which a sharp variation is periodically caused in load current, so that there is the possibility of occurrence of memory operation error and, further, system down due to activation of the overvoltage protection circuit of the DDC. Further, in the current balance circuit of the highest current mode, periodic variations in load current may cause an increase in output voltage. A new circuit method for solving these problems is desired.
In general, the following four modes are employed for the current balance circuit. They have respective characteristics and are used accordingly. In particular, of the four modes, the highest current mode is employed for the N+1 parallel redundant mode, which requires reliability, as described below.
The droop mode reduces output voltage by a certain amount when output current increases. This mode has a circuit configuration shown in FIG. 1, and is frequently employed in a front end bus power supply of 48 V or 12 V. However, this is not applied as the latest power supply for high-accuracy LSIs requiring low voltage and large current because of difficulty in ensuring voltage accuracy.
The master-slave mode, in which one DDC serves as a master and supplies a pulse signal to each slave DDC, is characterized by a simple circuit. However, when the master DDC fails, all the DDCs are down. Accordingly, this is not applied to the N+1 parallel redundant operation.
The average current mode, in which a DDC compares its current with the current of another DDC and finely adjusts output voltage based on their average, has a circuit configuration shown in FIG. 2. According to this mode, if one of multiple DDCs falls into an overcurrent pendent state or fails, current balance line voltage decreases so that the current balance function is lost. Accordingly, this is not applied to the N+1 parallel redundant operation.
The highest current mode has a circuit configuration shown in FIG. 3. In this mode, a DDC compares its current with a reference, which is the maximum one of the output current values of N DDCs operating in parallel, and balances its current (FIG. 2 of JP 7-194118 and FIG. 1 of Balogh).
According to this mode, by inserting a diode in the terminal part of a current share bus, a current sense amplifier is automatically detached from the bus when a DDC fails. As a result, even after this, the current balance function can be maintained among the remaining N DDCs. Accordingly, this mode is employed in the N+1 parallel redundant operation mode.
On the other hand, in recent years, there has occurred a problem in that when the above-described current balancing of the highest current mode is employed in POL, output voltage increases so as to cause memory operation error and, further, lead to system down.
FIG. 4 shows signal waveforms at the time of an output voltage increase actually generated in DDCs for memory in a server system.
DDC specifics in this case are as follows:
insulating card edge type;
switching frequency=600 kHz;
current mode;
highest current mode current balancing;
Vin=48 V;
Vout=2.5 V;
Iout=40 A; and
number of paralleled DDCs=3+1 parallel redundant operation.
Loads are 32 1-GB DDR memory cards, and a load capacitor is approximately 10,000 μF.
Other specifics are Vout=200 mV/D, Iout=0.5 V/D, and 50 mS/D.
FIG. 4 shows a 2.5 V output voltage waveform (CH4=Vout in the drawing) and the output current waveforms of the three DDCs (CH1, CH2, and CH3 in the drawing).
In the initial stage, the output current of each DDC is approximately 18 A, and the current balance function works normally. Thereafter, a load current varies in accordance with the operations of the DDR memory cards, but the output current follows up while balancing.
However, from about the fifth cycle, the output currents of the DDCs start to differ in size from and be out of phase with one another, and the output voltage starts to rise from 2.5 V, and finally, rises up to 3.3 V. As a result, an overvoltage protection circuit functions to stop the operation of each DDC, thus causing system down.
Such a phenomenon occurs only occasionally depending on conditions such as the arrangement of and the differences between DDCs and the number and the operation mode of DDR memory cards. Accordingly, it is difficult to discover its possibility with a test apparatus, and it is predicted that this phenomenon occurs in a field so as to result in a serious problem.
The mechanism of occurrence of this output voltage increase in the highest current mode is analyzed below based on circuit simulation results.
FIG. 5 shows a highest-current-mode current comparator circuit used in this analysis.
First, a discussion is made of the operation in the case where the load currents of DDCs vary in the same phase and in the same state.
Here, the Ishare terminal of each DDC is opened so as to cause the DDC to operate independently. The operation of the output voltage waveform Vad1 of the current comparator circuit is obtained by applying its own output current waveform V-Iout1 to the DDC.
FIG. 6A shows the operational waveform of the variation frequency of 2 kHz of V-Iout1 in a case where a resistor Rd is 200 kΩ in this case.
As shown in FIG. 6B, when the variation frequency of the output current is low, Vad1 operates normally without a voltage increase.
Next, FIG. 7A shows operational waveforms in the case of increasing the variation frequency by ten times to 20 kHz and successively changing the value of the resistor Rd from 500 kΩ to 200 kΩ and 10 kΩ.
As shown in FIG. 7A, when Rd is 200 kΩ, the voltage V-Ishare of the Ishare terminal is higher than V-Iout1 voltage for a longer period of time because the discharge speed of a capacitor Cg is lower than the variation of the output current. As a result, as shown in FIG. 7B, Vad1 increases because of the repeated variation of the output current.
When the value of the resistor Rd is set to 500 kΩ, Vad1 further increases (FIG. 7B). This increase in Vad1 results in an increase in the output voltage.
It is shown that next, when the value of the resistor Rd is reduced to 10 kΩ, the discharge speed of Cg becomes higher than the variation speed of V-Iout, so that it is possible to prevent Vad1 from increasing (FIGS. 7A and 7B).
It has been found that the problem of voltage increase can be improved by thus reducing the value of the resistor Rd connected in parallel to the capacitor Cg.
However, in the case of reducing the value of the resistor Rd, the following two problems occur.
The first one is that a forward drop in a diode D1 connected between the input terminals of a differential amplifier (adjustment amplifier) A1 increases so as to increase a differential input with respect to a current balancing operation. The second one is that a current flowing to the Ishare terminal increases so as to make it necessary to improve the driving capability of a current detection amplifier (current amplifier).
As a further increase in DDC operational frequencies and response speed is desired for the future, it will become necessary to increase the discharge speed of the capacitor Cg by further reducing the value of the resistor Rd. Accordingly, it is desired to solve these problems.
In the conventional centralized power system, a unit power supply, which is slow in response speed, is employed, and power is supplied to a load with a bus bar having a high inductance component. In this case, since the output impedance of the power supply rises from a low frequency domain, a large capacitor is added in the vicinity of the load. The inductance component and the load capacitor serve as filters so that the load current of the unit power supply becomes sinusoidal. As a result, overshoot and undershoot are kept low.
However, in the case of POL, connection line inductance is low, and the load capacitor is small. Accordingly, DDCs vary greatly in the inductance of their smoothing circuits, and differ greatly in the inductance and resistance of connection lines to the load. These elements may affect the output current waveforms of the DDCs.
As a result, an amplitude difference and a phase difference are generated between the overshoot and undershoot waveforms of the output currents of the DDCs as shown in FIG. 8. FIGS. 9A and 9B shows the operational waveforms of the current balance circuits of DDCs in the case where such output currents flow.
FIGS. 9A and 9B show the results of a simulation performed with application of a circuit configuration in which two circuits of FIG. 5 are connected.
FIGS. 9A and 9B show that the output voltage Vad1 of the comparator circuit increases because of the phase difference between the output currents of the two DDCs. In this case, reducing the value of the resistor Rd to 10 kΩ cannot completely solve the problem of output voltage increase generated because of variations in the load current.